1. Field of the Invention
This invention pertains generally to chip interconnection, and more particularly to a multi-band RF-interconnect transceiver as an advanced high-speed interface.
2. Description of Related Art
Chip-to-chip RF (radio-frequency) communication has become increasingly important to support exponential chip development advances with high pin counts and high complexity, that are increasingly difficult to distribute over traditional wired connections. In response to these interconnection problems, a number of solutions have been advanced for establishing RF chip-to-chip interconnections. One recent type of interconnection is directed at using a frequency-division multiple access interconnect (FDMA-I) transceiver for transmission line based multiple-band chip-to-chip communications.
However, although this interconnection mechanism provides a number of advantages, it suffers from power intensive phase and frequency synchronizations to demodulate binary phase-shift keying (BPSK) at the receiver, which increases transceiver architectural complexity, while requiring a large circuit area and a high overall power consumption. Consequently, this form of interconnection is not scalable and is not particularly well-suited for use in low power off-chip busses, such as those utilized within parallel memory busses.
Power and bandwidth requirements for dynamic random access memories (DRAMs) have continued becoming increasingly stringent. This is not surprising, in view of devices, such as mobile devices (e.g., smart phones) relying more intensively on graphics. The inputs and outputs (I/Os) of current double data rate (DDR) memory devices operate at approximately 5 Gb/s with a power efficiency of about 17.4 mW/Gb/s (i.e., 17.4 pJ/b). High-speed serial links provide an increased power efficiency of around 1 mW/Gb/s, which would be favorable for use in mobile memory I/O interfaces.
However, serial links typically suffer from the need of long initialization time, such as on the order of 1000 clock cycles, and do not meet mobile DRAM I/O requirements for fast switching between active, stand-by, self-refresh and power-down operating modes. In addition, traditional baseband-only (or BB-only) signaling tends to consume power super-linearly for extended bandwidth due to the need of power intensive pre-emphasis and equalization circuits.
Accordingly, the present invention provides apparatus and methods for overcoming wireless RF chip-to-chip interconnection issues with regard to power consumption, speed and circuit area, while being particularly well-suited for use in DRAM memory systems.